library verilog;
use verilog.vl_types.all;
entity IDDRXB is
    generic(
        REGSET          : string  := "RESET"
    );
    port(
        D               : in     vl_logic;
        ECLK            : in     vl_logic;
        SCLK            : in     vl_logic;
        CE              : in     vl_logic;
        LSR             : in     vl_logic;
        DDRCLKPOL       : in     vl_logic;
        QA              : out    vl_logic;
        QB              : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of REGSET : constant is 1;
end IDDRXB;
